The present invention relates to a method for manufacturing a semiconductor device, and particularly to a so-called damascene method for forming a copper wiring.
With improvements in the degree of integration and performance of each element employed in a recent semiconductor device, there has been a demand for miniaturization of wiring per se and further minimization of a wiring interval. With the progress of miniaturization in a manufacturing process, a wiring delay has rate-controlled an operating speed. Therefore, a copper wiring (forming) technique using a wiring material as copper (Cu) lower in resistance or a copper alloy has been developed. It is difficult to process copper (alloy) used as for the wiring material by an etching technique. Accordingly, a manufacturing method called “a so-called damascene method” has been adopted.
Described specifically, this damascene method is a method for forming wiring trenches in an insulating film, depositing a copper alloy thin film that buries the wiring trenches and thereafter polishing or grinding the copper alloy thin film from its upper side thereby to allow only portions for burying the wiring trenches to remain and form embedded wirings. A CMP (Chemical Mechanical Polishing) method is generally applied to the process of polishing such a copper alloy thin film.
With further progress toward miniaturization, the occurrence of so-called dishing becomes a problem in such a copper alloy technique. The dishing means a step formed by denting a wiring surface in a concave form.
The dishing occurs particularly in wiring difficult to make further reductions in wiring length, wiring width and wiring depth (thickness) even by the development of miniaturization of a wiring forming process as in the case of, for example, global wirings which function as, for example, a power supply wiring and a clock signal line. The occurrence of such dishing will cause a problem such as an increase in wiring resistance.
There has been disclosed a configuration wherein the thickness of a copper film to be deposited is set to 1.6 to 2.0 times the depth of a wiring trench with a view toward suppressing the occurrence of dishing by a CMP process (refer to, for example, a patent document 1 (Japanese Unexamined Patent Publication No. 2003-31577)).
According to the configuration disclosed in the patent document 1, however, there is a need to form the thickness of the copper (alloy) thin film thicker in order to prevent the so-called dishing. Accordingly, a problem arises in that the time required to perform the process of forming the copper alloy thin film and the polishing time required to carry out the process of polishing or grinding the copper alloy thin film increase, thus resulting in a reduction in throughput of a manufactured semiconductor device.
There has therefore been a desire for a technique for more efficiently forming wiring relatively large particularly in wiring width and wiring thickness, such as global wirings which function as, for example, a power supply wiring and a clock signal line, while preventing the dishing.